Ever increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 ‒ 10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer’s sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures. Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLLbased architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equally-spaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer. This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation. A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stage-delay mismatch, the static phase error of the locked-loop, and the duty cycle distortion of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer’s spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer’s behavioral and transistor-level model ina 65-nm CMOS process. Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieved by introducing an openloop compensation technique to keep the total delay-length of the delay line unchanged at the instant of band hopping. The relation between the compensation accuracy and the hopping speed is analyzed and formulated. In addition, to make the technique immune to process-voltage-temperature (PVT) variations, two calibration techniques are introduced. Furthermore, injection-locking technique is employed to reduce the total current consumption in the EC. The presented concept is supported by measurement results on a test chip implemented in a 65-nm CMOS process and achieves a worst-case sideband spur of ‒44 dBc and dissipates 21 mW of power at 1.2 V supply voltage. The second DLL-based synthesizer employs the concept of track-and-hold (T/H) technique to sample the lock control voltages and store them across the corresponding capacitors during a start-up phase. In normal operation, the loop control voltage is pre-charged to the corresponding stored voltage to perform fast channel switching. Since the presented architecture does not rely on the DLL bandwidth for fast switching, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples (which result in sideband spurs) is eliminated. Also, the delay line can be biased in low gain regions of its transfer function to reduce its noise amplification. The third DLL-based architecture merges the edge-combing and upconversion operations to achieve a low-power direct conversion IQ modulator based on subharmonic passive mixers and multiphase duty-cycled LO. The novelty of the architecture is in employing a quadrature mixer array in such a configuration that the upconversion of the baseband signal can be performed at a sub-harmonic of the LO. Therefore, the requirements on the frequency synthesizer circuitries and LO buffers are relaxed. In addition, since rail-to-rail clocks are provided easier at such low subharmonic frequencies, passive mixers are employed to further reduce the power dissipation and improve the linearity of the overall transmitter. Multiphase subharmonic LO clocks required by the proposed scheme are provided using a quadrature edge-combining DLL.
展开▼
